Flash memory has been widely applied to the data storage of digital products such as laptop computers, personal digital assistants, cellular telephones, digital cameras, digital recorders, and MP3 players. In order to keep up with customer demand for low-priced, efficient, small devices with high capacity, there is a growing need for highly integrated semiconductor memories. Accordingly, the use of 3-dimensional designs has been proposed for semiconductor memories. For example, conventional 3-dimensional memory designs such as Pipe-shaped Bit Cost Scalable (P-BiCS), Vertical Cell Array using TCAT (Terabit Cell Array Transistor), Vertical-Stacked-Array-Transistor (VSAT), and Vertical Gate NAND (VG-NAND) have been proposed to meet the growing need for highly integrated semiconductor memories.
However, there is a limitation on the conventional 3-dimensional memory designs. The conventional NAND flash memory cell uses the ONO (oxide-nitride-oxide) stack as the charge-trapping structure, wherein the oxide closest to the bitline determines the retention time, while the oxide closest to the wordline determines the tunneling selectivity, and the intervening nitride determines the charge-trapping capacity. In other words, the thickness of the ONO stack serving as the charge-trapping structure is not a scalable parameter, and the it is not feasible to increase the memory density of the conventional 3-dimensional memory designs by decreasing the thickness of the ONO stack. In addition, the conventional 3-dimensional memory designs implement the charge-trapping structure by the ONO stack laterally, requiring a very complicated fabrication process.